NAND devices are becoming more and more popular, and are starting to enter the embedded arena. That is expanding the range of voltage operation in such circuits from a typical 3 Volt range toward the 1.8 Volt range. For that region of operation, a Power On Reset (POR) circuit, which resets all circuits before the integrated circuit or NAND device begins to operate, has to fire at much lower voltages. Due to variation of process and temperature, the trip point of these circuits varies significantly, in some cases reaching the range of approximately 1 Volt. This is very low for reliable operation of memory circuits. Many configuration registers and other components need to be set at power up, including for example only and not by way of limitation redundant fuses, other functional fuses, or pins that need to be detected at power up that change the way the device communicates with the outside world.
The reading of fuses is at further risk because the current consumption of these types of memory devices is very low. In some cases, the current consumption is below one microampere. To read or configure such circuitry at very low voltages with very low currents is at best unreliable, and may cause many potential problems.
One of the problems with NAND devices is that since they have very low power consumption, on average less than one microampere, every or nearly every circuit must be shut off when they are not required for operations. Further, a problem with junction leakage exists. Having every circuit shut off is a problem because certain circuit elements, nodes, and devices require preconditioning before operation.
Several areas of difficulty are encountered in typical circuitry. Internal fuses are one. In many cases, fuses are read on power up. Internal fuses in a memory are used to set off voltages or other conditions inside the memory. With NOR cell technologies, during power up, circuit components, nodes, and the like are awakened with latches and the like. On power up, or on POR, one side of a latch is pulled down, which flips the latch. Referring to FIG. 1, a latch 100 with POR circuits 102 and program and erase circuitry 104 and 106 is shown. One input to the latch 100 is a program input, and one input to the latch is an erase input. During operation of a memory in which the latch and circuitry of FIG. 1 is used, the circuit of FIG. 1 is acceptable.
However, the POR must be low enough so that it never moves into the operating range of the device. In a circuit in which 1.5 Volts is the lowest Vcc range, this further limits POR voltages since there are inherent process variations and temperature variations of about three to four tenths of a Volt. In order, therefore, to keep POR out of the operating range of voltages, POR must be set around 1 volt. With threshold voltages in devices being high, on the order of 0.8 to 0.9 volts, the POR voltage is very close to the voltages when devices are turning on. Using POR to try to set voltages and configure startup conditions and preconditioning becomes very difficult, because if process margins move even a small amount, the fuses or circuitry may not read.
Other attempts at solving the problems with low operating voltages include eliminating POR altogether, as is shown in FIG. 2. In NAND devices, however, a single cell cannot perform the job since NAND is arranged in blocks. In such a configuration, a mini-array, of say 64 cells that are erase cells (element 202) and 64 cells that are program cells (element 204), are connected to the inputs of a latch 200. If all programming is erase programming, that latch side that drops to 0 should not be impacted. That is, the 64 cells that are erase will pull one side of the latch to 0, and the other side of the latch theoretically goes high, and there should be no current consumption. However, if there is even a slight leakage on any of the cells, a certain amount of current is pulled on one side that rapidly begins to consume the limited current of around 1 microampere.
Another proposal to fix the problems, especially those of FIG. 2, is shown in FIG. 3, in which there are pads 302 and 304 connected to ground through resistors 306 and 308. If nothing is touching the pads, they will both be low. When the pads are stacked, however, some may be connected to Vcc after stacking. If a pad is forced high, leakage problems still exist since a current is induced through the resistor, which once again begins to consume the limited current available.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a low current consumption operating NAND configuration.